1. Technical Field
Various embodiments of the present invention relate to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit that is capable of improving the reliability of a semiconductor integrated chip and related methods.
2. Related Art
Semiconductor integrated circuits have been developed toward high integration, high performance and low power consumption. As the degree of integration of semiconductor integrated circuits is increased, the internal operational voltage of semiconductor integrated chips have decreased accordingly.
To achieve this end, a package test on a chip in a semiconductor integrated circuit should be performed to monitor internal power voltages and force the voltages to target power levels so that the chip may perform normal operations or maintaining normal data.
Meanwhile, in the package test, the loading of a reference voltage (Vref) may be completed earlier than the loading of an external power voltage (VDD) while a power-up sequence is executed, or the reference voltage (Vref) may be applied earlier than the external power voltage (VDD), to an internal voltage terminal to be forced or monitored.
In this case, as the reference voltage having a level higher than that of a normal reference voltage is applied, the internal voltage which should be generated with a preset level may have a level higher than the preset level. As a consequence, the reliability of a semiconductor chip may be degraded which is problematic to the operation of the semiconductor integrated circuit.